The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-63153 filed on Mar. 8, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
The present invention relates to a ferroelectric memory (hereinafter called FeRAM) in which to array memory cells each consisting of a ferroelectric capacitor and a transistor.
The FeRAM is capable of storing data in a non-volatile way by making use of a hysteresis characteristic of the ferroelectric capacitor, and is electrically rewritable.
An EEPROM (Electrically Erasable Programmable Read Only Memory) using non-volatile memory cells based on a stack gate structure is known as a semiconductor memory which can store data in non-volatile manner and is electrically rewritable. The FeRAM exhibits, however, advantages in which FeRAM has a larger number of rewritable processes, a shorter writing time, a lower voltage capable operation and lower consumption electric power than the EEPROM.
Other difference between the EEPROM and FeRAM exist in that in the EEPROM, the data reading operation is a non-destructive reading process, whereas in the FeRAM the data is read by a destructive reading process. In more detail, in the case of the FeRAM, when a voltage for reading is applied to the ferroelectric capacitor, one of pieces of data of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d invariably involves an inversion of spontaneous polarization. Accordingly, after being read, there needs such a rewriting operation as to re-invert the inverted spontaneous polarization by the read data.
A discussion on the rewriting operation with reference to FIG. 4 will be made as follows. It is assumed that spontaneous polarizations Pr1, Pr2 each having the hysteresis characteristic of the ferroelectric capacitor are in a state where, for example, pieces of data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are stored. A positive voltage (e.g., a plate voltage) in FIG. 4 is applied to a ferroelectric capacitor, whereby a large quantity of signal electric charge occurs as indicated by a broken line with respect to the data xe2x80x9c0xe2x80x9d, and, when the voltage is set back to the previous level, there becomes a xe2x80x9c1xe2x80x9d data state where the spontaneous polarization is inverted. Namely, the destructive reading takes place.
With respect to the data xe2x80x9c1xe2x80x9d, since the signal electric charge quantity is small, and no polarization is not inverted. Thereafter, a negative voltage (e.g., a voltage supplied to a terminal electrode from a bit line) is applied to the ferroelectric capacitor, thereby rewriting the data xe2x80x9c0xe2x80x9d as indicted by the broken line.
In the FeRAM where the destructive reading described above is carried out, when read out in a state a internal voltage is not yet stabilized immediately after power on and when the voltage is applied to the ferroelectric capacitor, for instance, a correct value is not rewritten while the destructive reading is executed, and the data retained might be destructed.
In a DRAM, it is required in a specification or a standard that after switching on a power source, a pseudo access known as a dummy cycle must be carried out so as to wait till the voltage in each of the components of the memory falls within a range for an operation assurance.
In the case of the FeRAM, however, it is not enough that the dummy cycle is simply provided. Even when providing the dummy cycle, there exists a possibility in which the voltage is applied meanwhile to the ferroelectric capacitor that does not normally operate with the result that the data destruction occurs.
It is an object of the present invention, which was devised under such circumstances, to provide a ferroelectric memory capable of surely preventing a data destruction immediately after switching ON a power source and so on.
According to the one aspect of the present invention, there is provided a ferroelectric memory comprising:
a memory cell array having memory cells arrayed and each constructed of a ferroelectric capacitor and a transistor;
a decode circuit configured to select said memory cells of said memory cell array;
a sense amplifier circuit configured to detect and amplify data of a selected memory cell of said memory cell array selected by said decode circuit; and
an access permission circuit configured to output an access permission signal for permitting an access to said memory cell array when a predetermined period elapses after switching ON a power source.
According to another aspect of the present invention, there is provided a ferroelectric memory comprising:
a memory cell array having memory cells arrayed and each constructed of a ferroelectric capacitor and a transistor;
a decode circuit configured to select said memory cells of said memory cell array;
a sense amplifier circuit configured to detect and amplify data of a selected memory cell of said memory cell array selected by said decode circuit; and
an access permission circuit configured to output an access permission signal for permitting an access to said memory cell array after reaching a predetermined internal state.
The FeRAM according to the present invention is provided with an access permission circuit. The access permission circuit inhibits an access to a memory cell array during a period after switching on the power source. This contrivance makes it feasible to prevent a data destruction caused by applying a voltage in an unstable state to a ferroelectric capacitor.
According to the present invention, specifically, a counter for counting chip enable signals supplied from outside is provided. The access permission circuit detects that a count value of the counter reaches a predetermined value, and outputs the access permission signal. A chip internal state is thereby initialized to a normal state, and a dummy cycle for preventing the data destruction is set.
According to the present invention, the ferroelectric memory preferably has an internal power source circuit for generating an internal power source voltage by its being supplied with an external power source voltage, is provided. The access permission circuit detects that the internal power source voltage outputted by the internal power source circuit reaches a predetermined value, and outputs the access permission signal. It is therefore possible to prevent the data destruction caused by an operation in a state where the internal power source is unstable.
According to the present invention, the ferroelectric memory preferably comprises an internal power source circuit, having a function of switching a consumption current, for generating an internal power source voltage by the internal power source circuit being supplied with an external power source voltage. The internal power source circuit has a low consumption current during a standby state and is set, by the access permission signal outputted from the access permission circuit, in a state where the consumption current becomes larger than in the standby state. With this contrivance, the initialization of the internal voltage when switching ON the power source can be speeded up higher than before while restraining the consumption electric power when in the standby state, and a reliability when entering an active operation can be ensured.
According to the present invention, a specific mode of inhibiting the access is that at least one of the word line drive circuit and the plate line drive circuit is set in a drive signal output capable state by the access permission signal outputted from the access permission circuit. Alternatively, if a selective gate is provided between the memory cell array and the sense amplifier circuit, the selective gate drive circuit is activated by the access permission signal outputted from the access permission circuit. Further, an equalization circuit, activated when in a standby state, for equalizing a bit line of the memory cell array to a predetermined potential, is set inactive by the access permission signal outputted from the access permission circuit. The data destruction can be prevented by a proper combination of these modes.
Further, according to the present invention, a test area accessible irrespective of whether or not the access permission signal is given from the access permission circuit, is set in the memory cell array, and the access permission circuit judges a coincidence of test write data to the test area with read data therefrom, and outputs the access permission signal. With this contrivance, the accessibility can be obtained by confirming a voltage stable state with no data destruction.